[AArch64][GlobalISel] Add lowering for constant BIT/BIF/BSP #65897
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And this opcode needs a bit of documentation since it's not a real AArch64 instruction.
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At least some of this could be done with mi_match()? Not a big deal either way.
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I think you can just do MatchInfo = {v1,v2,v3};
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You can use GBuildVector::getSourceReg(k).
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I prefer *ValAndReg1 for ValAndReg2 precedence is not obvious.
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for (int k = 0, int NumElements = DstTy.getNumElements(); k < NumElements; ++k)
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In the far future a scalable vector might sneak in, then you cannot walk over its members.
The non-constant versions already work through tablegen patters, this mirrors the basic support for or(and(X, C), and(Y, ~C)) from ISel tryCombineToBSL. BSP gets expanded to either BIT, BIF or BSL depending on the best register allocation. G_BIT can be replaced with G_BSP as a more general alternative.
davemgreen
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Hi @davemgreen, I am seeing flang/clang failures in the llvm-test-suite after this patch with tests involving copy sign:
Can you check if this is related to your patch that involves copy sign on aarch64? |
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Hello. It sounds like it might be related. I might not have updated the existing copysign code correctly, as I was planning to remove it eventually. I will revert and take a look. |
The non-constant bit/bif/bsp already work through tablegen patterns, this patch handles the constant case, mirroring the basic support for `or(and(X, C), and(Y, ~C))` from ISel tryCombineToBSL. BSP gets expanded to either BIT, BIF or BSL depending on the best register allocation. G_BIT can be replaced with G_BSP as a more general alternative.
The non-constant bit/bif/bsp already work through tablegen patterns, this patch handles the constant case, mirroring the basic support for `or(and(X, C), and(Y, ~C))` from ISel tryCombineToBSL. BSP gets expanded to either BIT, BIF or BSL depending on the best register allocation. G_BIT can be replaced with G_BSP as a more general alternative.
The non-constant bit/bif/bsp already work through tablegen patterns, this patch handles the constant case, mirroring the basic support for `or(and(X, C), and(Y, ~C))` from ISel tryCombineToBSL. BSP gets expanded to either BIT, BIF or BSL depending on the best register allocation. G_BIT can be replaced with G_BSP as a more general alternative.
The non-constant bit/bif/bsp already work through tablegen patterns, this patch handles the constant case, mirroring the basic support for `or(and(X, C), and(Y, ~C))` from ISel tryCombineToBSL. BSP gets expanded to either BIT, BIF or BSL depending on the best register allocation. G_BIT can be replaced with G_BSP as a more general alternative.
The non-constant bit/bif/bsp already work through tablegen patterns, this patch handles the constant case, mirroring the basic support for `or(and(X, C), and(Y, ~C))` from ISel tryCombineToBSL. BSP gets expanded to either BIT, BIF or BSL depending on the best register allocation. G_BIT can be replaced with G_BSP as a more general alternative.
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I have been making my way through GlobalISel vector fp, making sure all the basic types are currently working. In looking at fcopysign I managed to rewrite it in a way that we just widen to vectors, as opposed to relying on custom lowering. That misses handling vector constants (which Mark here is currently looking at) and transforming
or/andintobit.The non-constant bit/bif/bsp already work through tablegen patters, this patch handles the constant case, mirroring the basic support for
or(and(X, C), and(Y, ~C))from ISel tryCombineToBSL. BSP gets expanded to either BIT, BIF or BSL depending on the best register allocation. G_BIT can be replaced with G_BSP as a more general alternative.